The present invention relates, generally, to digital processors, and more specifically, to a multi-function timer with shared hardware for microprocessor-based engine control applications.
Micro-sequencers have commonly been used to sequence through instructions and data for processor usage in a digital system, such as a computer-based system. A difficulty of multiple digital signal input/output functionality implemented by a single micro-sequencer has been the ability of the sequencer to process multiple inputs/outputs with a high degree of resolution. The resolution is generally limited by the instruction throughput of the sequencer coupled with the complexity of the input/output functions. This limitation may result in a latency to reacting to a new input/output events while processing the most current event.
Current systems have typically dedicated a single algorithm in hardware to a single pin in a digital system. Also, in order to utilize different algorithms on the same pin, some systems have stored all potential algorithms with a pin and selection of only one of the algorithms is assigned to the pin. One disadvantage with these systems is that only one algorithm may be utilized on the input/output data at the pin. In other words, in systems such as microprocessor-based engine control systems, separate, dedicated circuits are used to generate multiple timed output events on dedicated output pins, and to perform multiple input timing measurements on dedicated input pins. Disadvantages of such systems include limited design flexibility in terms of die size, pin usage and hardware. Also, another disadvantage is that there is wasted circuitry hardware in the case of multiple algorithms on a selected pin in that only one algorithm will be utilized.